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Dynamically Reconfigurable Networks-on-Chip: We investigate multicore reconfigurable processors with dynamic adaptation to changing work loads and operating environments. The processing elements and interconnect standard FPGA fabrics enhanced with fast partial dynamic reconfiguration and adaptive voltage scaling. The communication infraextructure uses packet-based communication based on the SpaceWire standard with adaptive topologies and routing to deliver fault-tolerance. The analysis investigates the effects of data packets freely intermixed with configuration packets destined to the processing elements. We are developing a number of optimized processing engines to demonstrate the benefits of this platform in a multimedia application. An example of one of this engines is the LiquidMotion processor with a base configuration available to download at http://opencores.org/project,motion_estimation_processor

Energy efficient computing with reconfigurable chips: Future microprocessors face an energy efficiency challenge as the move towards deeply integrated multi-core heterogeneous architectures increases transistor counts. The combination of general purpose CPUs and reconfigurable fabrics (FPGAs) to increase the computational power beyond what is possible with CPUs or GPUs constitute an area of a lot of research interest. Reconfigurable fabrics allow the customization of the hardware microarchitecture but a limitation of the approach is that they are high-power and this can result in high electricity bills or make them unsuitable for battery power applications. Our research in energy efficiency investigates principles of energy proportional computing using our adaptive voltage and frequency scaling technology called Elongate so that the device can regulate its own energy comsumption. The research also looks into ways to optimize the external memory bottleneck with high-performance lossless compression/decompression with dedicated hardware engines. An example of our compressor core called X-MatchPRO can be downloaed for free at : http://opencores.org/project,xmatchpro.

Energy optimization with ARM big.LITTLE heterogenous processors : The objective of this project is to investigate design-time and run-time system-level techniques that can be combined to reduce the energy footprint of heterogenous processors that combine binary compatible cores of different complexity (e.g. Cortex A15+A7 present in ARM big.LITTLE). More specifically energy optimization techniques could consider power models based on linear and non-linenar regression for the different system components, the activity measurements that can drive these power models and how the models can be parametric in function of different voltage, frequencies and system capacitance. Then these models can be used at run-time techniques to predict energy requirements in commercial applications and how system state can be adjusted in function of these predictions to match energy availability and demand.

Arithmetic coder architecture.

The LiquidMotion configurable/programmable motion estimation processor
(http://uk.youtube.com/watch?v=TkRnm8qvdDA to see me working !) or visit (http://sharpeye.borelspace.com/) to download the latest version of the processor generation tools.

Comparison between nominal and optimized energy (7x lower) in a Xilinx Virtex-5 device deploying the Elongate adaptive voltage scaling technology.

Power models for a motion estimation processor implemented in the PL side of a ZYNQ device.