Workshop on next-generation hardware for high-performance computing (NG-HPC 2018)

Next-gen hardware for performance and energy efficiency

Part of the Marionet UK Many-core Research Network



The workshop is free to attend and thanks to the Marionet network lunch and coffee are included. More information about the Marionet many-core network can be found here:


The only requirement is to register using the links below so we can sort out the cattering.

Information about the venue can be found following this link: venue

Information about the university of Bristol location and how to get here can be found following this link : here









Registration deadline: 1st September , 2018,

Workshop date 11th September 2018







The workshop will be held in the Lower Atrium, room 1.11, MVB Building, Woodland Road, Department of Electrical and Electronic Engineering, University of Bristol, BS8 1UB. More information about the program can be found following the link on the left. If you would like to partcipate as a speaker please let us know at this e_mail with a topic and a short bio ( We would do our best to accomodate you subject to time constraints. To register attendance please follow this link: registration