Workshop on next-generation hardware for high-performance computing
(NG-HPC 2018) Bristol, 11th September

Next-gen hardware for performance and energy efficiency

Part of the Marionet UK Many-core Research Network

Performance and power issues in conventional HPC hardware have resulted in significant efforts done in new accelerator hardware designs and new ways to use available hardware originally not designed for HPC. Examples include novel use of embedded multi-core CPUs and hardware accelerators based on GPUs and FPGAs. Domain specific CPU architectures capable of delivering performance and ease of programmability are also the focus of intensive research and development together with innovative programming models and algorithms exploiting HPC hardware or software. The demand of techniques to handle the debugging and optimization of these systems are also increasing as the human capability of understanding complex software/hardware interactions reaches its limit.

 

This workshop aims at being a forum to learn, network and discuss about recent progress in this field. The objective is to have an interesting set of presentations from leading industrialists and academics. The workshop will consist of a series of invited talks to present novel hardware architectures and novel use of that hardware to obtain high-performance and energy efficiency. Topics of interest include when computation is performed with a combination of different core types such as GPUs (Graphics Processing Units), CPUs (Central Processing Unit) and FPGAs (Field Programmable Gate Arrays) and also be formed with cores capable of executing a common instruction set but with different performance levels and energy requirements. Programming models able to target these different computing resources with a single piece of code are also relevant as new ways to understand behaviours observed in these complex devices. The workshop has no registration fee but pre-registration is required for catering purposes. Refreshments and lunch will be provided and are sponsored by the Marionet workshop.

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IMPORTANT DATES :

Registration deadline: 1st September , 2018,

Workshop date 11th September 2018

 

 

 

 

 

 

The workshop will be held in the Lower Atrium, room 1.11, MVB Building, Woodland Road, Department of Electrical and Electronic Engineering, University of Bristol, BS8 1UB. More information about the program can be found following the link on the left. If you would like to partcipate as a speaker please let us know at this e_mail with a topic and a short bio (j.l.nunez-yanez@bristol.ac.uk). We would do our best to accomodate you subject to time constraints. To register attendance please follow this link: registration

 

 

 

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