Workshop on next-generation hardware for high-performance computing (NG-HPC 2018)

Next-gen hardware for performance and energy efficiency

Part of the Marionet UK Many-core Research Network

 

Program chair :

Dr Jose Nunez-Yanez, University of Bristol

 

Technical commitee :

Professor Simon McIntosh-Smith, University of Bristol

 

Professor Kestin Eder, University of Bristol

 

Dr Jeremy Singer, University of Glasgow

 

 

 

Carlo Luschi, Graphcore Carlo is Director of Research at Graphcore, where he is responsible for the study and development of machine learning algorithms. He was a Member of Technical Staff at Bell Labs Research, Lucent Technologies, and more recently Director of Algorithms and Standards at Icera Inc., and Director of Algorithms and Standards at NVIDIA. Carlo has a PhD from the University of Edinburgh, and holds 55 patents granted or pending.

Adrian Tate, Cray UK, Adrian is the Director of the Cray EMEA Research Lab (CERL), a specialist organisation in Cray dealing with deep technical collaboration. The purpose of CERL is to develop longer-term relationships with customers and partners to help address massive challenges in system design and usage, and to ultimately help Cray to build future products. Some examples of the challenges we are addressing are integration of AI and HPC, memory hierarchy usage within data-intensive applications, HPC + Analytics workflow optimisation.

Gajinder Panesar, UltraSoC UK, Gajinder Panesar is currently the CTO of UltraSoC Technologies Ltd. A company providing semiconductor IP that can be added to any SoC to provide run-time visibility of the whole system. Gajinder’s experience includes senior architecture definition and design roles within both blue-chip and start-up environments. He holds more than 20 patents and is the author of more than 20 published works. Prior to joining UltraSoC, he served at NVIDIA (NASDAQ:NVDA). As Chief Architect at Picochip he created the architecture of the company’s market-defining small-cell SoCs, and continued in this capacity after the company’s acquisition by Mindspeed Inc (NASDAQ:MSPD). His previous experience includes roles at STMicroelectronics, INMOS, and Acorn Computers. He is a former Research Fellow at the UK’s Southampton University, and a former Visiting Fellow at the University of Amsterdam.

Jahanzeb Ahmad, Intel, Vision Design Engineer. Jahanzeb Ahmad joined Intel Programmable Solutions Group (PSG) formally known as Altera in 2013 and is currently working as vision design engineer. His current responsibilities include architecting and developing machine learning architectures and solutions for autonomous vehicles and surveillance. Prior to joining PSG, Jahanzeb did his PhD in computer vision and medical engineering from University of The West of England, Bristol, UK.

Dr. Christos Bouganis Imperial College. Christos received the M.Eng degree in Computer Engineering and Informatics from University of Patras Greece in 1998, the MSc degree in Communications and Signal Processing in 1999 and the Ph.D. degree in 2004 both from Imperial College London. He joined the Department of Electrical and Electronic Engineering as academic faculty in 2007. He is currently a Reader within Department of Electrical and Electronic Engineering and is also the Director of the MSc in Analogue and Digital Integrated Circuit Design. His research inlcudes the theory and practice of reconfigurable computing and design automation, mainly targeting digital signal processing algorithms. His work is currenlty focused on Computer Vision and Image Processing, Machine Learning, Markov Chain Monte Carlo Systems, and computing with unreliable harwdare.

Anna Brown, Research Software Engineer, Oxford Eresearch Center, Ania is a research software engineer with a background in physics. Her research interests are a combination of performance optimisation for large scale scientific simulation and software development methodology to improve the quality of such codes. She was completing her Master's degree at the Tokyo Institute of Technology, working on optimising the adaptive mesh algorithm for use on Graphical Processing Units (GPUs).

 

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