[1] J. Mouro, S. Rana, J. D. Reynolds, H. M. H. Chong, and D. Pamunuwa, “Estimating the surface adhesion force using pull-in/ -out hysteresis in comb-drive devices,” in Proc. Transducers, Jun. 2019, pp. -. [ bib ]
[2] J. D. Reynolds, S. Rana, J. Mouro, D. Pamunuwa, and H. M. H. Chong, “4-terminal lateral mems silicon relay with nanocrystalline graphite contact and polymer insulating mechanical coupler,” in Proc. Int. Conf. Solid State Devices and Materials, 2019, pp. -. [ bib ]
[3] D. Pamunuwa, “Heterogeneous 3-D integration of NEMS and ICs, Micro- and Nano-Engineering (MNE) conference,” Nov. 2018, invited presentation, Nov 25, Copenhagen, Denmark. [Online]. Available: http://mne2018.org/Program/bib | http ]
[4] T. Qin, S. J. Bleiker, S. Rana, F. Niklaus, and D. Pamunuwa, “Performance analysis of nanoelectromechanical relay-based field-programmable gate arrays,” IEEE Access, vol. 6, pp. 15997-16009, 2018. [Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8318576&isnumber=8274985bib | DOI | http ]
[5] S. Rana, J. D. Reynolds, T. Y. Ling, M. S. Shamsudin, S. H. Pu, H. M. Chong, and D. Pamunuwa, “Nano-crystalline graphite for reliability improvement in MEM relay contacts,” Carbon, vol. 133, pp. 193-199, 2018. [Online]. Available: https://www.sciencedirect.com/science/article/pii/S0008622318302549bib | DOI | http ]
[6] H. Dymond, J. Wang, D. Liu, J. Dalton, N. McNeill, D. Pamunuwa, S. Hollis, and B. Stark, “A 6.7-GHz active gate driver for GaN FETs to combat overshoot, ringing, and EMI,” IEEE Trans. Power Electronics, vol. 33, no. 1, pp. 581-594, 2018. [ bib | DOI ]
[7] J. D. Reynolds, S. Rana, Y. L. Ting, L. A. Boodhoo, S. H. Pu, D. Pamunuwa, and H. M. H. Chong, “Nanocrystalline graphite coatings for lateral silicon mems transistors,” in Proc. International Conference on Micro and Nano Engineering (MNE), Sep. 2017, pp. -. [ bib | DOI ]
[8] J. Dalton, J. Wang, H. C. Dymond, D. Liu, D. Pamunuwa, N. McNeill, S. Hollis, and B. Stark, “Shaping switching waveforms in a 650 V GaN FET bridge-leg using 6.7 GHz active gate drivers,” in Proc. IEEE Applied Power Electronics Conference and Exposition (APEC), Mar. 2017, pp. 1983-1989. [ bib | DOI ]
[9] S. Rana and Pamunuwa, “Moment-driven bifurcated non-volatile nano-electromechanical relay,” Patent, 2017, UK Patent 1 721 670.6, filed Dec 21 2017. [ bib ]
[10] S. Rana, D. Pamunuwa, and S. Chong, “Nanoelectromechanical (NEM) relay with nanocrystalline graphite (ncg) coating,” Patent, 2017, UK patent No. 1604254.1, granted 16th Mar 2017. [ bib ]
[11] D. Pamunuwa, “Nanoelectromechanical (NEM) relay-based circuits for high-temperature and radiation-hard electronics,” Nov. 2016, Invited talk, Nov. 30, Southampton University, Southampton UK. [ bib ]
[12] L. Boodhoo, S. Rana, J. Reynolds, Y. Tsuchiya, W. Redman-White, S. H. Pu, H. Mitzuta, D. Pamunuwa, and H. M. H. Chong, “Nano-crystalline graphite coated SOI NEMS switches,” in Proc. Int. Microprocesses and Nanotechnology Conf., Nov. 2016. [ bib ]
[13] H. C. Dymond, D. Liu, J. Wang, J. Dalton, N. McNeill, D. Pamunuwa, S. Hollis, and B. Stark, “Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-impedance patterns,” in Proc. IEEE Energy Conversion Congress and Exposition (ECCE), Jul. 2016, pp. -, Best paper award. [ bib | DOI ]
[14] D. Pamunuwa, “Nanoelectromechanical (NEM) relay-based computing,” Jul. 2016, Invited seminar, July 13, Institute for Computer Technology, Technical University of Vienna, Austria. [Online]. Available: https://www.ict.tuwien.ac.at/en/aktuelles/news/guest-lecture-nanoelectromechanical-relay%E2%80%90based-computingbib | http ]
[15] D. Pamunuwa, “Nano-electro-mechanical relays for RADiation resistant and high-temperature operation - NEMRAD,” Apr. 2016, Invited presentation, April 27, UK Centre for Defence Enterprise (CDE) Marketplace Event, Royal Society, London UK. [ bib ]
[16] D. Pamunuwa, “Micro/nanoelectromechanical relays for digital logic applications,” Dec. 2015, Invited seminar, Dec 3, Centre for Nanoscience and Quantum Information (NSQI), University of Bristol, UK. [ bib ]
[17] T. Qin, S. Rana, and D. Pamunuwa, “Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2015, pp. 641-648. [ bib | DOI ]
[18] A. Y. Weldezion, M. Grange, A. Jantsch, H. Tenhunen, and D. Pamunuwa, “Zero-load predictive model for performance analysis in deflection routing NoCs,” Microprocessors and Microsystems, vol. 39, no. 8, pp. 634-647, Nov. 2015. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0141933115001428bib | DOI | http ]
[19] D. Pamunuwa, “Nanoelectromechanical (NEM) relay-based computing,” Jul. 2015, Invited talk, July 09, UK-Japan Silicon Nanoelectronics & Nanotechnology (UK-Japan Si NANO2) Symposium, Southampton UK. [ bib ]
[20] S. Rana, Q. Tian, A. Bazigos, D. Grogg, M. Despont, C. L. Ayala, C. Hagleitner, A. M. Ionescu, R. Canegallo, and D. Pamunuwa, “Energy and latency optimization in NEM relay-based digital circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2348-2359, Aug. 2014. [ bib | DOI ]
[21] A. Bazigos, C. L. Ayala, M. Fernandez-Bolanos, Y. Pu, D. Grogg, C. Hagleitner, S. Rana, T. T. Qin, D. Pamunuwa, and A. M. Ionescu, “Analytical compact model in Verilog-A for electrostatically actuated ohmic switches,” IEEE Transactions on Electron Devices, vol. 61, no. 6, pp. 2186-2194, Jun. 2014. [ bib | DOI ]
[22] A. Bazigos, C. L. Ayala, S. Rana, D. Grogg, M. Fernandez-Bolaños, C. Hagleitner, T. Qin, D. Pamunuwa, and A. M. Ionescu, “Electromechanical design space exploration for electrostatically actuated ohmic switches using extended parallel plate compact model,” Solid-State Electronics, vol. 99, pp. 93-100, 2014. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0038110114001634bib | DOI | http ]
[23] A. Y. Weldezion, M. Grange, D. Pamunuwa, A. Jantsch, and H. Tenhunen, “A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns,” in Proc. IEEE International 3D Systems Integration Conference (3DIC), Oct. 2013, pp. 1-5. [ bib | DOI ]
[24] D. Pamunuwa, “System performance analysis for heterogeneous 3-D ICs and emerging technologies,” Jul. 2013, Invited talk, June 26, Design for 3D Silicon Integration Workshop (D43D), Grenoble France. [ bib ]
[25] S. Rana, T. Qin, D. Grogg, M. Despont, Y. Pu, C. Hagleitner, and D. Pamunuwa, “Modelling NEM relays for digital circuit applications,” in Proc. IEEE International Conference on Circuits and Systems (ISCAS), May 2013, pp. 805-808. [ bib | DOI ]
[26] “Investigating nano-electro-mechanical relay-based computing,” EE Times Europe, Sep. 2012, please note that Dr. Dinesh Pamunuwa is a Reader in Microelectronics at the University of Bristol, and not a Lecturer in Nanotechnology at Lancaster University as stated erroneously in the article. [Online]. Available: http://mag.electronics-eetimes.com/EETE_SEPTEMBER_2012/pubData/source/EETimes%20Sdeptember%202012.pdfbib | .pdf ]
[27] “IBM, ST go back to the future with nanorelay logic,” 2012. [Online]. Available: http://www.eetimes.com/document.asp?doc_id=1262443bib | http ]
[28] M. Grange, A. Jantsch, R. Weerasekera, and D. Pamunuwa, “Modeling the computational efficiency of 2-d and 3-d silicon processors for early chip planning,” in Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2011, pp. 310-317. [ bib | DOI ]
[29] D. Pamunuwa, M. Grange, R. Weerasekera, and A. Jantsch, “3-d integration and the limits of silicon computation,” in Proc. IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Oct. 2011, pp. 343-348, Invited Presentation, Special Session on Frontier in 3-D Integrated Engineering, Hong Kong. [ bib | DOI ]
[30] D. Pamunuwa, “ELITE - Extended large (3-d) integration technology,” Sep. 2011, Introductory Keynote at Workshop, European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland. [ bib ]
[31] M. Grange, R. Weerasekera, D. Pamunuwa, A. Jantsch, and A. Y. Weldezion, “Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks,” in Proc. ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011, pp. 57-64. [ bib | DOI ]
[32] M. Grange, A. Jantsch, R. Weerasekera, and D. Pamunuwa, “Modeling the efficiency of stacked silicon systems: Computational, thermal and electrical performance,” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2011, pp. 14-18. [ bib ]
[33] R. Weerasekera, D. Pamunuwa, M. Grange, A. Jantsch, A. Richardson, and M. Scannel, “Comparative cost analysis of 3-d integrated circuits,” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2011. [ bib ]
[34] A. C. Fischer, M. Grange, N. Roxhed, R. Weerasekera, D. Pamunuwa, G. Stemme, and F. Niklaus, “Wire-bonded through-silicon vias with low capacitive substrate coupling,” Journal of Micromechanics and Microengineering, vol. 21, no. 8, p. 085035, 2011. [Online]. Available: http://stacks.iop.org/0960-1317/21/i=8/a=085035bib | http ]
[35] A. Jantsch, M. Grange, and D. Pamunuwa, “The promises and limitations of 3-d integration,” in 3D Integration for NoC-based SoC Architectures, ser. Integrated Circuits and Systems, A. Sheibanyrad, F. Pétrot, and A. Jantsch, Eds. Springer New York, 2011, pp. 27-44. [Online]. Available: http://dx.doi.org/10.1007/978-1-4419-7618-5_2bib | DOI | http ]
[36] M. Grange, R. Weerasekera, and D. Pamunuwa, “Optimal signaling techniques for through silicon vias in 3-d integrated circuit packages,” in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2010, pp. 237-240. [ bib | DOI ]
[37] R. Weerasekera, M. Grange, D. Pamunuwa, and H. Tenhunen, “On signalling over through-silicon via (tsv) interconnects in 3-d integrated circuits,” in Proc. Conference on Design, Automation and Test in Europe, Mar. 2010, pp. 1325-1328. [ bib | DOI ]
[38] M. Grange, A. Y. Weldezion, D. Pamunuwa, R. Weerasekera, Z. Lu, A. Jantsch, and D. Shippen, “Physical mapping and performance study of a multi-clock 3-dimensional network-on-chip mesh,” in Proc. IEEE International Conference on 3D System Integration (3DIC), Sep. 2009, pp. 1-7. [ bib | DOI ]
[39] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.-R. Zheng, “Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-d) integrated circuits,” in Proc. IEEE International Conference on 3D System Integration (3DIC), Sep. 2009, pp. 1-8. [ bib | DOI ]
[40] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 28, no. 8, pp. 1237-1250, Aug. 2009. [ bib | DOI ]
[41] C. Lei, D. Pamunuwa, S. Bailey, and C. Lambert, “Design of robust molecular electronic circuits,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp. 1819-1822. [ bib | DOI ]
[42] A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, and H. Tenhunen, “Scalability of network-on-chip communication architecture for 3-d meshes,” in Proc. ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2009, pp. 114-123. [ bib | DOI ]
[43] A. Weldezion, R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Bandwidth optimization for through-silicon via (TSV) bundles in 3-d integrated circuits,” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2009. [ bib ]
[44] M. Grange, R. Weerasekera, D. Pamunuwa, and H. Tenhunen, “Examination of delay and signal integrity metrics in through-silicon vias,” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2009. [ bib ]
[45] M. Grange, R. Weerasekera, D. Pamunuwa, and H. Tenhunen, “Exploration of through-silicon via interconnect parasitics for 3-dimensional integrated circuits,” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2009. [ bib ]
[46] R. Weerasekera, D. B. Pamunuwa, M. Grange, H. Tenhunen, and L.-R. Zheng, “Closed-form equations for through-silicon via (TSV) parasitics in 3-d integrated circuits (ICs),” in Workshop Notes, Special Interest Workshop on 3D Integration - Design Automation and Test in Europe (DATE), Apr. 2009. [ bib ]
[47] C. Lei, D. Pamunuwa, S. Bailey, and C. Lambert, “Designing reliable digital molecular electronic circuits,” in Nano-Net, ser. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, A. Schmid, S. Goel, W. Wang, V. Beiu, and S. Carrara, Eds. Springer Berlin Heidelberg, 2009, vol. 20, pp. 111-115. [Online]. Available: http://dx.doi.org/10.1007/978-3-642-04850-0_17bib | DOI | http ]
[48] C. Lei, D. Pamunuwa, S. Bailey, and C. Lambert, “Application of molecular electronics devices in digital circuit design,” in Nano-Net, ser. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, M. Cheng, Ed. Springer Berlin Heidelberg, 2009, vol. 3, pp. 61-65. [Online]. Available: http://dx.doi.org/10.1007/978-3-642-02427-6_12bib | DOI | http ]
[49] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 589-593, May 2008. [ bib | DOI ]
[50] D. Pamunuwa, “Memory technology for extended large-scale integration in future electronics applications,” in Proc. Design, Automation and Test in Europe Conference (DATE), Mar. 2008, pp. 1126-1127, Invited Presentation, Hot Topic Session. [ bib | DOI ]
[51] R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “Extending systems-on-chip to the third dimension: Performance, cost and technological tradeoffs,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007, pp. 212-219. [ bib | DOI ]
[52] R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “Early selection of system implementation choice among SoC, SoP and 3-D integration,” in Proc. IEEE International Conference on Systems-on-Chip (SOC), Sep. 2007, pp. 187-190. [ bib | DOI ]
[53] C. Lei, D. B. Pamunuwa, S. Bailey, and C. Lambert, “Molecular electronics device modeling for system design,” in Proc. IEEE International Conference on Nanotechnology (IEEE-NANO), Aug. 2007. [ bib | DOI ]
[54] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Delay-balanced smart repeaters for on-chip global signaling,” in Proc. IEEE International Conference on VLSI Design, Jan. 2007, pp. 308-313. [ bib | DOI ]
[55] D. Pamunuwa and R. Weerasekera, “Nanodevices: from novelty toys to functional devices - an integration perspective,” in Proc. IEEE International Conference on Industrial and Information Systems, Aug. 2006, Invited Presentation. [ bib | DOI ]
[56] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime,” in Proc. International Workshop on System-Level Interconnect Prediction (SLIP), May 2006, pp. 113-120. [ bib | DOI ]
[57] D. Pamunuwa, S. Elassaad, and H. Tenhunen, “Modeling delay and noise in arbitrarily-coupled rc trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 11, pp. 1725-1739, Nov. 2005. [ bib | DOI ]
[58] T. Nurmi, J. Liu, D. Pamunuwa, T. Ahonen, L.-R. Zheng, J. Isoaho, and H. Tenhunen, “Global interconnect analysis,” in Interconnect-Centric Design for Advanced SoC and NoC, J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Eds. Springer US, 2005, pp. 55-84. [Online]. Available: http://dx.doi.org/10.1007/1-4020-7836-6_3bib | DOI | http ]
[59] R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “Switching sensitive driver circuit to combat dynamic delay in on-chip buses,” in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, ser. Lecture Notes in Computer Science, V. Paliouras, J. Vounckx, and D. Verkest, Eds. Springer Berlin Heidelberg, 2005, vol. 3728, pp. 277-285. [Online]. Available: http://dx.doi.org/10.1007/11556930_29bib | DOI | http ]
[60] R. Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “Crosstalk immune interconnect driver design,” in Proc. IEEE International Symposium on System-on-Chip (SOC), Nov. 2004, pp. 139-142. [ bib | DOI ]
[61] D. Pamunuwa, J. Ã–berg, L.-R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen, “A study on the implementation of 2-d mesh-based networks-on-chip in the nanometre regime,” Integration, the VLSI Journal, vol. 38, no. 1, pp. 3 - 17, 2004. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0167926004000203bib | DOI | http ]
[62] D. Pamunuwa, “Modelling and analysis of interconnects for deep submicron systems-on-chip,” Ph.D. dissertation, Kungl Tekniska Högskolan (Royal Institite of Technology), Stockholm, Sweden, Dec. 2003. [Online]. Available: http://www.diva-portal.org/smash/get/diva2:9493/FULLTEXT01.pdfbib | .pdf ]
[63] D. Pamunuwa, S. Elassaad, and H. Tenhunen, “Analytic modeling of interconnects for deep sub-micron circuits,” in Pro. IEEE/ACM International Conference on Computer-aided design, Nov. 2003, p. 835. [ bib | DOI ]
[64] D. Pamunuwa and S. Elassaad, “Closed-form metrics to accurately model the response in general arbitrarily-coupled rc trees,” in Proc. IEEE International Symposium on Circuits and Systems, (ISCAS), vol. 4, May 2003, pp. IV-604. [ bib | DOI ]
[65] J. Liu, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “A global wire planning scheme for network-on-chip,” in Proc. IEEE International Symposium on Circuits and Systems, (ISCAS), vol. 4, May 2003, pp. IV-892. [ bib | DOI ]
[66] D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Maximizing throughput over parallel wire structures in the deep submicrometer regime,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, pp. 224-243, Apr. 2003. [ bib | DOI ]
[67] D. Pamunuwa, S. Elassaad, and H. Tenhunen, “Modelling noise and delay in vlsi circuits,” Electronics Letters, vol. 39, no. 3, pp. 269-271, Feb. 2003. [ bib | DOI ]
[68] D. Pamunuwa, J. Öberg, L.-R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen, “Layout, performance and power trade-offs in mesh-based network-on-chip architectures,” in Proc. IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2003, p. 362. [ bib ]
[69] D. Pamunuwa and L.-R. Zheng, “Signalling techniques for dsm designs,” Sep. 2002, Tutorial at European Solid-State Circuits Conference, Florence Italy. [ bib ]
[70] H. Tenhunen and D. Pamunuwa, “On dynamic delay and repeater insertion,” in Proc. IEEE International Symposium on Circuits and Systems, (ISCAS), vol. 1, May 2002, pp. I-97. [ bib | DOI ]
[71] D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Optimising bandwidth over deep sub-micron interconnect,” in Proc. IEEE International Symposium on Circuits and Systems, (ISCAS), vol. 4, May 2002, pp. IV-193. [ bib | DOI ]
[72] D. Pamunuwa and H. Tenhunen, “On dynamic delay and repeater insertion in distributed capacitively-coupled interconnects,” in Proc. International Symposium on Quality Electronic Design, (ISQED), Mar. 2002, pp. 240-245. [ bib | DOI ]
[73] D. Pamunuwa and H. Tenhunen, “Repeater insertion to minimise delay in coupled interconnects,” in Proc. IEEE International Conference on VLSI Design, Jan. 2001, pp. 513-517. [ bib | DOI ]
[74] L.-R. Zheng, D. B. Pamunuwa, and H. Tenhunen, “Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron vlsi design,” in Proc. European Solid-State Circuits Conference, Sep. 2000. [ bib ]
[75] D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Combating digital noise in high speed ULSI circuits using binary bch encoding,” in Proc. IEEE International Symposium on Circuits and Systems, (ISCAS), vol. 4, May 2000, pp. 13-16. [ bib | DOI ]
[76] D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Error-control coding to combat digital noise in interconnects for ulsi circuits,” in Proc. IEEE NORCHIP Conference, 1999, pp. 275-282. [ bib ]

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